Different ESD input/output protection networks, based on Zener diodes and lateral npn transistors, have been implemented with the aim of characterizing their effectiveness in protecting vertical DMOS power transistors. Failure mechanisms have been indented by means of static emission microscopy, Gated emissions microscopy, in synchronism with a voltage pulse emulating the ESD event, enables the dynamic behavior of protection structures to be analyzed, identifying lateral current crowding effects which explain the observed failure mechanism.
Analysis of ESD protection networks for DMOS power transistors by means of static and time-resolved emission microscopy / B., Bonati; A., Canclini; M., Cavone; E., Novarini; Pavan, Paolo; R., Rivoir; M., Stucchi; E., Zanoni. - In: QUALITY AND RELIABILITY ENGINEERING INTERNATIONAL. - ISSN 0748-8017. - STAMPA. - 9:(1993), pp. 315-319. (Intervento presentato al convegno ESREF'92 tenutosi a Stuttgart, D nel 5-8 October 1992).
Analysis of ESD protection networks for DMOS power transistors by means of static and time-resolved emission microscopy
PAVAN, Paolo;
1993
Abstract
Different ESD input/output protection networks, based on Zener diodes and lateral npn transistors, have been implemented with the aim of characterizing their effectiveness in protecting vertical DMOS power transistors. Failure mechanisms have been indented by means of static emission microscopy, Gated emissions microscopy, in synchronism with a voltage pulse emulating the ESD event, enables the dynamic behavior of protection structures to be analyzed, identifying lateral current crowding effects which explain the observed failure mechanism.
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