Reduction of the gate leakage current in nMOS high-k devices is demonstrated by an engineered two-step deposited Hf-based high-k dielectric film. The electrical characteristics and reliability of the devices fabricated using the proposed two-step and conventional one-step high-k gate stacks are shown to be comparable. The lower leakage current is attributed to the misalignment of the grain boundaries in the multi-layer high-k dielectrics.
Gate Leakage Current Reduction in Two-Step Processed High-k Dielectrics for Low Power Applications / G., Bersuker; D., Heh; J., Huang; C. S., Park; Padovani, Andrea; Larcher, Luca; P., Kirsch; R., Jammy. - ELETTRONICO. - (2010), pp. 1034-1035. (Intervento presentato al convegno International Conference on Solid State Devices and Materials (SSDM) tenutosi a Tokyo, Japan nel 22-24 September 2010).
Gate Leakage Current Reduction in Two-Step Processed High-k Dielectrics for Low Power Applications
PADOVANI, ANDREA;LARCHER, Luca;
2010
Abstract
Reduction of the gate leakage current in nMOS high-k devices is demonstrated by an engineered two-step deposited Hf-based high-k dielectric film. The electrical characteristics and reliability of the devices fabricated using the proposed two-step and conventional one-step high-k gate stacks are shown to be comparable. The lower leakage current is attributed to the misalignment of the grain boundaries in the multi-layer high-k dielectrics.
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