This paper proposes a comparison of the two most advanced algorithms for connected components labeling, highlighting how they perform on a soft core SoC architecture based on FPGA. In particular we test our block based connected components labeling algorithm, optimized with decision tables and decision trees. The embedded system is composed of the CMOS image sensor, FPGA, DDR SDRAM, USB controller and SPI Flash. Results highlight the importance of caching and instructions and data cache sizes for high performance image processing tasks.
High Performance Connected Components Labeling on FPGA / Grana, Costantino; Borghesani, Daniele; Santinelli, Paolo; Cucchiara, Rita. - STAMPA. - (2010), pp. 221-225. (Intervento presentato al convegno First International Workshop Interactive Multimodal Pattern Recognition in Embedded Systems tenutosi a Bilbao, Spain nel Sep 1) [10.1109/DEXA.2010.57].
High Performance Connected Components Labeling on FPGA
GRANA, Costantino;BORGHESANI, Daniele;SANTINELLI, PAOLO;CUCCHIARA, Rita
2010
Abstract
This paper proposes a comparison of the two most advanced algorithms for connected components labeling, highlighting how they perform on a soft core SoC architecture based on FPGA. In particular we test our block based connected components labeling algorithm, optimized with decision tables and decision trees. The embedded system is composed of the CMOS image sensor, FPGA, DDR SDRAM, USB controller and SPI Flash. Results highlight the importance of caching and instructions and data cache sizes for high performance image processing tasks.
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