The purpose of this paper is to illustrate a physically-based model allowing the statistical simulations of oxide leakage currents in MOS transistors and Floating Gate memories. This model computes the leakage current through defects randomly generated in the oxide, in case accounting for the formation of percolation paths. Furthermore, a calculation procedure has been developed to calculate the threshold voltage of FG memories from simulated oxide leakage currents in some reliability conditions, thus allowing to investigate their actual Flash data retention issues and their future trends. To this regards, it will be shown how this simulation model can be used to investigate threshold voltage shift occurring in retention conditions in FG memories after both Program/erase cycles, i.e. electrical stress and radiation exposure.

Statistical Simulations of Oxide Leakage Current in MOS Transistors and Floating Gate Devices / Larcher, Luca; Pavan, Paolo. - ELETTRONICO. - (2005), pp. 117-122. ((Intervento presentato al convegno 2005 Workshop on Compact Modeling tenutosi a Anaheim, CA (USA) nel MAY 8-12.

Statistical Simulations of Oxide Leakage Current in MOS Transistors and Floating Gate Devices

LARCHER, Luca;PAVAN, Paolo
2005

Abstract

The purpose of this paper is to illustrate a physically-based model allowing the statistical simulations of oxide leakage currents in MOS transistors and Floating Gate memories. This model computes the leakage current through defects randomly generated in the oxide, in case accounting for the formation of percolation paths. Furthermore, a calculation procedure has been developed to calculate the threshold voltage of FG memories from simulated oxide leakage currents in some reliability conditions, thus allowing to investigate their actual Flash data retention issues and their future trends. To this regards, it will be shown how this simulation model can be used to investigate threshold voltage shift occurring in retention conditions in FG memories after both Program/erase cycles, i.e. electrical stress and radiation exposure.
2005 Workshop on Compact Modeling
Anaheim, CA (USA)
MAY 8-12
117
122
Larcher, Luca; Pavan, Paolo
Statistical Simulations of Oxide Leakage Current in MOS Transistors and Floating Gate Devices / Larcher, Luca; Pavan, Paolo. - ELETTRONICO. - (2005), pp. 117-122. ((Intervento presentato al convegno 2005 Workshop on Compact Modeling tenutosi a Anaheim, CA (USA) nel MAY 8-12.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/466474
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