EnglishThe latch-up phenomenon in CMOS ICs is studied by means of a SEM observation technique that is based on capacitively coupled voltage contrast and is characterized by digital beam control and image acquisition. Passivated devices are studied at low beam energies, without interfering with their electrical behavior. The comparison between images taken in the latched and nonlatched state allows reliable identification of the latch-up current paths and thus of the latched site. The performance of the technique is demonstrated by three examples which refer to one standard and two custom CMOS ICs.
| Anno di pubblicazione: | 1986 |
| Titolo: | Observation of latch-up phenomena in CMOS IC's by means of Digital Differential Voltage Contrast |
| Autore/i: | F. FANTINI; M.VANZI; C.MORANDI; E.ZANONI |
| Autore/i UNIMORE: | |
| Rivista: | |
| Volume: | 21 |
| Pagina iniziale: | 169 |
| Pagina finale: | 174 |
| Codice identificativo Scopus: | 2-s2.0-0022670575 |
| Citazione: | Observation of latch-up phenomena in CMOS IC's by means of Digital Differential Voltage Contrast / F. FANTINI; M.VANZI; C.MORANDI; E.ZANONI. - In: IEEE JOURNAL OF SOLID-STATE CIRCUITS. - ISSN 0018-9200. - STAMPA. - 21(1986), pp. 169-174. |
| Tipologia | Articolo su rivista |
File in questo prodotto:
Non ci sono file associati a questo prodotto.
I documenti presenti in Iris Unimore sono rilasciati con licenza Creative Commons Attribuzione - Non commerciale - Non opere derivate 3.0 Italia, salvo diversa indicazione.
In caso di violazione di copyright, contattare Supporto Iris
Copyright © 2019