(EPROM)-P-2 memory devices are widely used in embedded applications. For an efficient design flow, a correct modeling of these memory cells in every operation condition becomes more and more important, especially due to power consumption limitations. Although (EPROM)-P-2 cells are being used for a long time, very few compact models have been developed. Here, we present a complete compact model based on an original procedure to calculate the floating gate Potential in dc conditions, without the need of any capacitive coupling coefficient. This model is designed as a modular structure, so to simplify program/erase and reliability simulations. Program/erase and leakage currents are included by means of simple voltage-controlled current sources implementing their analytical expression. It can be used to simulate memory cells both during read operation (dc conditions) and during program and erase (transient conditions) giving always very accurate results. We will show also that, provided good descriptions of degradation mechanisms, the same model can be used also for reliability simulations, predicting charge loss due to tunnel oxide degradation.
|Anno di pubblicazione:||2003|
|Titolo:||A complete model of (EPROM)-P-2 memory cells for circuit simulations|
|Autori:||P. Pavan; L. Larcher; M. Cuozzo; P. Zuliani; A. Conte|
|Appare nelle tipologie:||Articolo su rivista|
File in questo prodotto:
I documenti presenti in Iris Unimore sono rilasciati con licenza Creative Commons Attribuzione - Non commerciale - Non opere derivate 3.0 Italia, salvo diversa indicazione.
In caso di violazione di copyright, contattare Supporto Iris