This work is aimed at proposing a standard procedure for moderately accelerated Electromigration (EM) tests applied to interconnection lines of the present and the next future generation of integrated circuits. The procedure has been tested on one metal level test structures using an AI-alloy metallization scheme, but can be easily applied to other materials as well as to metal lines with vias. Different existing standards have been taken into consideration to define this proposal: ASTM F1260-89, JEDEC JESD33-A, JESSI AC41. In the PROPHECY project, the focus was on wafer level reliability evaluation with fast methods, but fast EM methods using extremely accelerated stress conditions usually induce side-effects which can invalidate the results. As a consequence, this procedure suggests the use of moderately accelerated tests, together with a method for reducing the number of tests needed for a complete EM characterization. This procedure gives advice on the test structures to be used and on the preliminary steps to be performed before the EM tests. A measurement system, complying with the requirements of this procedure, is also briefly described. The methods described in this document apply to both package- and wafer-level measurements. In order to validate this procedure, EM tests have been performed on JESSI AC41 specimens. (C) 1999 Elsevier Science Ltd. All rights reserved.
|Anno di pubblicazione:||1999|
|Titolo:||A proposal for a standard procedure for moderately accelerated electromigration tests on metal lines|
|Autore/i:||A. Scorzoni; M. Impronta; I. De Munari; F. Fantini|
|Codice identificativo ISI:||WOS:000082296800007|
|Codice identificativo Scopus:||2-s2.0-0032642550|
|Tipologia||Articolo su rivista|
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