Channel-Side Interlayer Engineering in Laminated Fe-FETs: Trap-Driven Optimization of Memory Window, Retention, and Disturb in Ferroelectric NAND Flash

In this work, we demonstrate for the first time that laminated Fe-FETs for Fe-NAND exhibit a distinct behavior: despite the common expectation that higher-k channel-side interlayers (C-ILs) enhance reliability by lowering the equivalent oxide thickness (EOT), lower-k C-ILs instead deliver superior memory-window (MW), retention, and pass-disturb performance. We systematically compare three different pure-oxide C-ILs (SiO2,Al2O3,HfO2) through experiments and TCAD modeling to elucidate trap-driven reliability. The results reveal that although high- k C-IL layer reduce EOT, their higher trap densities cause MW narrowing, faster retention loss, and enhanced charge trapping. Devices with an 8 nmHf0.5Zr0.5O2/3 nmAl2O3/8 nmHf0.5Zr0.5O2 stack and 1.5 nm C-ILs confirm that the low k oxide achieves the most stable operation, exhibiting 15% larger MW, 1% retention loss at 1 ks, and 44% lower electron-trapping-induced disturb degradation after 106 passdisturb cycles. This behavior arises from trap-induced charges that outweighs the expected benefit of high dielectric constant, as confirmed by TCAD simulations. These findings highlight C-IL trap engineering as a key enabler for reliable, high-density FeNAND integration and clarify how channel IL-dependent traps govern reliability in laminated Fe-FETs.