Experimental demonstration of robust high temperature operation with 10 4 endurance and stable V Th at 125 °C enabled by IL scavenging in Si Channel FEFETs

Endurance degradation in conventional Si-Channel ferroelectric FETs (FEFETs) is predominantly governed by trap generation within the interfacial SiO₂ (IL) layer, where elevated electric fields accelerate defect generation, leading to polarization screening and progressive memory window (MW) collapse. In this work, we demonstrate that using scavenging to thin the IL layer induces a sub-stoichiometric SiOx, with higher capacitance which dramatically improves the endurance characteristics of the FEFET. This IL engineering results in a redistribution of voltage and a new mode of FEFET failure driven by the underlying FE rather than the IL. This FE-driven degradation paradigm yields three critical advantages: (1) suppression of subthreshold slope (SS) deterioration by minimizing interface state buildup, (2) MW stability over extended cycling, as evidenced by a stable high-VTh and low-VTh states until FE breakdown, and (3) reduction in read-after-write latency due to faster de-trapping of traps in IL layer. We also demonstrate robust MW at 125°C with 104 cycles endurance and low SS. Further, we quantify trap generation and electric fields in the IL and FE layers using Ginestra™ simulations. These findings establish an innovative and efficient pathway to high endurance, stable VTh FEFETs via the implementation of an IL engineering-driven control of ferroelectric degradation.