Like most high-end embedded systems, FPGA-based systems-on-chip (SoC) are increasingly adopting heterogeneous designs, where CPU cores, the configurable logic and other ICs all share interconnect and main memory (DRAM) controller. This paradigm is scalable and reduces production costs and time-to-market, but creates resource contention issues, which ultimately affects the programs' timing. This problem has been widely studied on CPU- and GPU-based systems, along with strategies to mitigate such effects, but little has been done so far to systematically study the problem on FPGA-based SoCs. This work provides an in-depth analysis of memory interference on such systems, tar-geting two state-of-the-art commercial FPGA SoCs. We also discuss architectural support for Controlled Memory Request Injection (CMRI), a technique that has proven effective at reducing the bandwidth under-utilization implied by naive schemes that solve the interference problem by only allowing mutually exclusive access to the shared resources. Our experimental results show that: i) memory interference can slow down CPU tasks by up to 16×in the tested FPGA-based SoCs; ii) CMRI allows to exploit more than 40% of the memory bandwidth avail-able to FPGA accelerators (normally completely unused in PREM-like schemes), keeping the slowdown due to interference below 10%.

Understanding and Mitigating Memory Interference in FPGA-based HeSoCs / Brilli, G.; Capotondi, A.; Burgio, P.; Marongiu, A.. - (2022), pp. 1335-1340. ((Intervento presentato al convegno 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 tenutosi a Virtual, Online nel 14 - 23 March 2022 [10.23919/DATE54114.2022.9774768].

Understanding and Mitigating Memory Interference in FPGA-based HeSoCs

Brilli G.;Capotondi A.;Burgio P.;Marongiu A.
2022-01-01

Abstract

Like most high-end embedded systems, FPGA-based systems-on-chip (SoC) are increasingly adopting heterogeneous designs, where CPU cores, the configurable logic and other ICs all share interconnect and main memory (DRAM) controller. This paradigm is scalable and reduces production costs and time-to-market, but creates resource contention issues, which ultimately affects the programs' timing. This problem has been widely studied on CPU- and GPU-based systems, along with strategies to mitigate such effects, but little has been done so far to systematically study the problem on FPGA-based SoCs. This work provides an in-depth analysis of memory interference on such systems, tar-geting two state-of-the-art commercial FPGA SoCs. We also discuss architectural support for Controlled Memory Request Injection (CMRI), a technique that has proven effective at reducing the bandwidth under-utilization implied by naive schemes that solve the interference problem by only allowing mutually exclusive access to the shared resources. Our experimental results show that: i) memory interference can slow down CPU tasks by up to 16×in the tested FPGA-based SoCs; ii) CMRI allows to exploit more than 40% of the memory bandwidth avail-able to FPGA accelerators (normally completely unused in PREM-like schemes), keeping the slowdown due to interference below 10%.
2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022
Virtual, Online
14 - 23 March 2022
1335
1340
Brilli, G.; Capotondi, A.; Burgio, P.; Marongiu, A.
Understanding and Mitigating Memory Interference in FPGA-based HeSoCs / Brilli, G.; Capotondi, A.; Burgio, P.; Marongiu, A.. - (2022), pp. 1335-1340. ((Intervento presentato al convegno 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 tenutosi a Virtual, Online nel 14 - 23 March 2022 [10.23919/DATE54114.2022.9774768].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1280820
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