Presence of defects in high-k dielectric materials will affect device's electrical properties, thus, defect/material characterization is of great importance. We present a simulation-based methodology relying on an accurate description of charge trapping and transport that is useful to extract relevant information on material and defect characteristics. This methodology was applied to cerium oxide and lanthanum oxide high-k dielectric materials and as a result, material properties alongside defect characteristics were extracted. Consequently, main charge conduction mechanism was identified to be trap-assisted tunneling (TAT).

Multiscale modeling of CeO2/La2 O3 stacks for material/defect characterization / Dianat, B.; Padovani, A.; Larcher, L.. - 2020-:(2020), pp. 1-3. (Intervento presentato al convegno 33rd IEEE International Conference on Microelectronic Test Structures, ICMTS 2020 tenutosi a gbr nel 2020) [10.1109/ICMTS48187.2020.9107922].

Multiscale modeling of CeO2/La2 O3 stacks for material/defect characterization

Dianat B.;Padovani A.;Larcher L.
2020

Abstract

Presence of defects in high-k dielectric materials will affect device's electrical properties, thus, defect/material characterization is of great importance. We present a simulation-based methodology relying on an accurate description of charge trapping and transport that is useful to extract relevant information on material and defect characteristics. This methodology was applied to cerium oxide and lanthanum oxide high-k dielectric materials and as a result, material properties alongside defect characteristics were extracted. Consequently, main charge conduction mechanism was identified to be trap-assisted tunneling (TAT).
2020
33rd IEEE International Conference on Microelectronic Test Structures, ICMTS 2020
gbr
2020
2020-
1
3
Dianat, B.; Padovani, A.; Larcher, L.
Multiscale modeling of CeO2/La2 O3 stacks for material/defect characterization / Dianat, B.; Padovani, A.; Larcher, L.. - 2020-:(2020), pp. 1-3. (Intervento presentato al convegno 33rd IEEE International Conference on Microelectronic Test Structures, ICMTS 2020 tenutosi a gbr nel 2020) [10.1109/ICMTS48187.2020.9107922].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1249292
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