Understanding the Impact of Annealing on Interface and Border Traps in the Cr/HfO2/Al2O3/MoS2 System

Top-gated, few-layer MoS2 transistors with HfO2 (6 nm)/Al2O3 (3 nm) gate dielectric stacks are fabricated and electrically characterized by capacitance-voltage (C-V) measurements to study electrically active traps (D-it) in the vicinity of the Al2O3/MoS2 interface. Devices with low D-it and high D-it are both observed in C-V characterization, and the impact of H-2/N-2 forming gas annealing at 300 and 400 degrees C on the D-it density and distribution is studied. A 300 degrees C anneal is able to reduce the D-it significantly, while the 400 degrees C anneal increases defects in the gate stack. Simulation with modeled defects suggests a sizable decrease in D-it, half the amount of positive fixed charge in the dielectric, and slightly increased unintentional doping in MoS2 after a 300 degrees C anneal. In the as-fabricated devices displaying high D-it levels, the energy distribution of the D-it located at the Al2O3/MoS2 interface is continuous from the conduction band edge of MoS2 down to 0.13-0.35 eV below the conduction band edge. A plausible D-it origin in our experiments could come from the unexpected oxygen atoms that fill the sulfur vacancies during the UV-O-3 functionalization treatment. The border trap concentration in Al2O3 is the same, both before and after the anneal, suggesting a different origin of the border traps, possibly due to the low-temperature atomic-layer-deposited process.