Despite exceeding the Baliga's Figure of Merit (BFOM) by 400% and Huang's Chip Area Manufacturing FOM (HCAFOM) by 330% [1], the performance of existing β-Ga 2 O 3 FETs is inferior to that of GaN, primarily due to extreme self-heating. Self-heating effect (SHE) has emerged as an important concern for device performance, output power density, run-time variability and reliability for modern logic transistors. The effects are even more severe for high-power transistor where the channel material may be a poor thermal conductor, e.g. β-Ga 2 O 3 . Very high internal electric fields, extreme temperature and mechanical stresses associated with these transistors drive electrochemical reactions [2], influence atomic processes [3], and accelerate multiple non-equilibrium effects [4]. A device-circuit-package, multi-physics, multi-scale simulation is needed to capture these effects self-consistently, but such a model has not yet been developed. In this paper, we (i) develop the first self-consistent device (TCAD), circuit (HSPICE), and package (COMSOL) model considering SHE which predicts FET performance on variety of substrates accurately; (ii) use the model to propose a novel hexagonal-Boron Nitride (h-BN) based β-Ga 2 O 3 FET with 30% (cf. Sapphire substrate) and 80% (cf. SiO 2 substrate) reduction in thermal resistance (R th ); (iii) demonstrate the performance of boost converter (with parameters extracted from our TCAD model) with h-BN based β-Ga 2 O 3 FET, which outperforms the existing β-Ga 2 O 3 FETs, achieving an efficiency within 10-15% of highest performing enhancement mode (E-mode) GaN FET; (iv) propose h-BN based FinFET which exceeds the I ON of the existing β-Ga 2 O 3 FET by more than 500%; and (v) develop a Faraday-cage type novel packaging strategy for effective heat dissipation and efficient system performance in β-Ga 2 O 3 FETs.

Design and Optimization of β-Ga 2 O 3 on (h-BN layered) Sapphire for High Efficiency Power Transistors: A Device-Circuit-Package Perspective / Mahajan, B. K.; Chen, Y. -P.; Ahn, W.; Zagni, N.; Alam, M. A.. - (2018), pp. 24.6.1-24.6.4. ((Intervento presentato al convegno 64th Annual IEEE International Electron Devices Meeting, IEDM 2018 tenutosi a San Francisco, California, USA nel 2018 [10.1109/IEDM.2018.8614714].

Design and Optimization of β-Ga 2 O 3 on (h-BN layered) Sapphire for High Efficiency Power Transistors: A Device-Circuit-Package Perspective

Zagni N.;
2018

Abstract

Despite exceeding the Baliga's Figure of Merit (BFOM) by 400% and Huang's Chip Area Manufacturing FOM (HCAFOM) by 330% [1], the performance of existing β-Ga 2 O 3 FETs is inferior to that of GaN, primarily due to extreme self-heating. Self-heating effect (SHE) has emerged as an important concern for device performance, output power density, run-time variability and reliability for modern logic transistors. The effects are even more severe for high-power transistor where the channel material may be a poor thermal conductor, e.g. β-Ga 2 O 3 . Very high internal electric fields, extreme temperature and mechanical stresses associated with these transistors drive electrochemical reactions [2], influence atomic processes [3], and accelerate multiple non-equilibrium effects [4]. A device-circuit-package, multi-physics, multi-scale simulation is needed to capture these effects self-consistently, but such a model has not yet been developed. In this paper, we (i) develop the first self-consistent device (TCAD), circuit (HSPICE), and package (COMSOL) model considering SHE which predicts FET performance on variety of substrates accurately; (ii) use the model to propose a novel hexagonal-Boron Nitride (h-BN) based β-Ga 2 O 3 FET with 30% (cf. Sapphire substrate) and 80% (cf. SiO 2 substrate) reduction in thermal resistance (R th ); (iii) demonstrate the performance of boost converter (with parameters extracted from our TCAD model) with h-BN based β-Ga 2 O 3 FET, which outperforms the existing β-Ga 2 O 3 FETs, achieving an efficiency within 10-15% of highest performing enhancement mode (E-mode) GaN FET; (iv) propose h-BN based FinFET which exceeds the I ON of the existing β-Ga 2 O 3 FET by more than 500%; and (v) develop a Faraday-cage type novel packaging strategy for effective heat dissipation and efficient system performance in β-Ga 2 O 3 FETs.
2018
64th Annual IEEE International Electron Devices Meeting, IEDM 2018
San Francisco, California, USA
2018
24.6.1
24.6.4
Mahajan, B. K.; Chen, Y. -P.; Ahn, W.; Zagni, N.; Alam, M. A.
Design and Optimization of β-Ga 2 O 3 on (h-BN layered) Sapphire for High Efficiency Power Transistors: A Device-Circuit-Package Perspective / Mahajan, B. K.; Chen, Y. -P.; Ahn, W.; Zagni, N.; Alam, M. A.. - (2018), pp. 24.6.1-24.6.4. ((Intervento presentato al convegno 64th Annual IEEE International Electron Devices Meeting, IEDM 2018 tenutosi a San Francisco, California, USA nel 2018 [10.1109/IEDM.2018.8614714].
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11380/1184588
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