Many applications require both high performance and predictable timing. High-performance can be provided by COTS Multi-Core System on Chips (MPSoC), however, as cores in these systems share main memory, they are susceptible to interference from each other, which is a problem for timing predictability. We achieve predictability on multi-cores by employing the predictable execution model (PREM), which splits execution into a sequence of memory and compute phases, and schedules these such that only a single core is executing a memory phase at a time. We present a toolchain consisting of a compiler and a scheduling tool. Our compiler uses region and loop based analysis and performs tiling to transform application code into PREM-compliant binaries. In addition to enabling predictable execution, the compiler transformation optimizes accesses to the shared main memory. The scheduling tool uses a state-of-the-art heuristic algorithm and is able to schedule industrial-size instances. For smaller instances, we compare the results of the algorithm with optimal solutions found by solving an integer linear programming model. Furthermore, we solve the problem of scheduling execution on multiple cores while preventing interference of memory phases. We evaluate our toolchain on Advanced Driver Assistance System (ADAS) application workloads running on an NVIDIA Tegra X1 embedded system-on-chip (SoC). The results show that our approach maintains similar average performance to the original (unmodified) program code and execution, while reducing variance of completion times by a factor of 9 with the identified optimal solutions and by a factor of 5 with schedules generated by our heuristic scheduler.

Combining PREM compilation and static scheduling for high-performance and predictable MPSoC execution / Matejka, J.; Forsberg, B.; Sojka, M.; Sucha, P.; Benini, L.; Marongiu, A.; Hanzalek, Z.. - In: PARALLEL COMPUTING. - ISSN 0167-8191. - 85:(2019), pp. 27-44. [10.1016/j.parco.2018.11.002]

Combining PREM compilation and static scheduling for high-performance and predictable MPSoC execution

Marongiu A.;
2019

Abstract

Many applications require both high performance and predictable timing. High-performance can be provided by COTS Multi-Core System on Chips (MPSoC), however, as cores in these systems share main memory, they are susceptible to interference from each other, which is a problem for timing predictability. We achieve predictability on multi-cores by employing the predictable execution model (PREM), which splits execution into a sequence of memory and compute phases, and schedules these such that only a single core is executing a memory phase at a time. We present a toolchain consisting of a compiler and a scheduling tool. Our compiler uses region and loop based analysis and performs tiling to transform application code into PREM-compliant binaries. In addition to enabling predictable execution, the compiler transformation optimizes accesses to the shared main memory. The scheduling tool uses a state-of-the-art heuristic algorithm and is able to schedule industrial-size instances. For smaller instances, we compare the results of the algorithm with optimal solutions found by solving an integer linear programming model. Furthermore, we solve the problem of scheduling execution on multiple cores while preventing interference of memory phases. We evaluate our toolchain on Advanced Driver Assistance System (ADAS) application workloads running on an NVIDIA Tegra X1 embedded system-on-chip (SoC). The results show that our approach maintains similar average performance to the original (unmodified) program code and execution, while reducing variance of completion times by a factor of 9 with the identified optimal solutions and by a factor of 5 with schedules generated by our heuristic scheduler.
85
27
44
Combining PREM compilation and static scheduling for high-performance and predictable MPSoC execution / Matejka, J.; Forsberg, B.; Sojka, M.; Sucha, P.; Benini, L.; Marongiu, A.; Hanzalek, Z.. - In: PARALLEL COMPUTING. - ISSN 0167-8191. - 85:(2019), pp. 27-44. [10.1016/j.parco.2018.11.002]
Matejka, J.; Forsberg, B.; Sojka, M.; Sucha, P.; Benini, L.; Marongiu, A.; Hanzalek, Z.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11380/1179007
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