Simulators are still the primary tools for development and performance evaluation of applications running on massively parallel architectures. However, current virtual platforms are not able to tackle the complexity issues introduced by 1000-core future scenarios. We present a fast and accurate simulation framework targeting extremely large parallel systems by specifically taking advantage of the inherent potential processing parallelism available in modern GPGPUs.
Scalable instruction set simulator for thousand-core architectures running on GPGPUs / Raghav, S.; Ruggiero, M.; Atienza, D.; Pinto, C.; Marongiu, A.; Benini, L.. - (2010), pp. 459-466. (Intervento presentato al convegno High Performance Computing and Simulation (HPCS), 2010 International Conference on tenutosi a Caen nel June 28 2010-July 2 2010) [10.1109/HPCS.2010.5547092].
Scalable instruction set simulator for thousand-core architectures running on GPGPUs
MARONGIU A.;
2010
Abstract
Simulators are still the primary tools for development and performance evaluation of applications running on massively parallel architectures. However, current virtual platforms are not able to tackle the complexity issues introduced by 1000-core future scenarios. We present a fast and accurate simulation framework targeting extremely large parallel systems by specifically taking advantage of the inherent potential processing parallelism available in modern GPGPUs.
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