The deployment of real-time workloads on commercial off-the-shelf (COTS) hardware is attractive, as it reduces the cost and time-to-market of new products. Most modern high-end embedded SoCs rely on a heterogeneous design, coupling a general-purpose multi-core CPU to a massively parallel accelerator, typically a programmable GPU, sharing a single global DRAM. However, because of non-predictable hardware arbiters designed to maximize average or peak performance, it is very difficult to provide timing guarantees on such systems. In this work we present our ongoing work on GPUguard, a software technique that predictably arbitrates main memory usage in heterogeneous SoCs. A prototype implementation for the NVIDIA Tegra TX1 SoC shows that GPUguard is able to reduce the adverse effects of memory sharing, while retaining a high throughput on both the CPU and the accelerator.

GPUguard: Towards supporting a predictable execution model for heterogeneous SoC / Forsberg, B., Marongiu, A., Benini, L.. - ELETTRONICO. - (2017), pp. 318-321. (20th Design, Automation and Test in Europe, DATE 2017 SwissTech Convention Center, che 2017) [10.23919/DATE.2017.7927008].

GPUguard: Towards supporting a predictable execution model for heterogeneous SoC

Marongiu, Andrea;
2017

Abstract

The deployment of real-time workloads on commercial off-the-shelf (COTS) hardware is attractive, as it reduces the cost and time-to-market of new products. Most modern high-end embedded SoCs rely on a heterogeneous design, coupling a general-purpose multi-core CPU to a massively parallel accelerator, typically a programmable GPU, sharing a single global DRAM. However, because of non-predictable hardware arbiters designed to maximize average or peak performance, it is very difficult to provide timing guarantees on such systems. In this work we present our ongoing work on GPUguard, a software technique that predictably arbitrates main memory usage in heterogeneous SoCs. A prototype implementation for the NVIDIA Tegra TX1 SoC shows that GPUguard is able to reduce the adverse effects of memory sharing, while retaining a high throughput on both the CPU and the accelerator.
2017
Inglese
20th Design, Automation and Test in Europe, DATE 2017
SwissTech Convention Center, che
2017
Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017
318
321
4
9783981537093
Institute of Electrical and Electronics Engineers Inc.
345 E 47TH ST, NEW YORK, NY 10017 USA
Computer Networks and Communications; Hardware and Architecture; Safety; Risk; Reliability and Quality
Forsberg, Bjorn; Marongiu, Andrea; Benini, Luca
Atti di CONVEGNO::Relazione in Atti di Convegno
273
3
GPUguard: Towards supporting a predictable execution model for heterogeneous SoC / Forsberg, B., Marongiu, A., Benini, L.. - ELETTRONICO. - (2017), pp. 318-321. (20th Design, Automation and Test in Europe, DATE 2017 SwissTech Convention Center, che 2017) [10.23919/DATE.2017.7927008].
partially_open
info:eu-repo/semantics/conferenceObject
   High-Performance Real-time Architectures for Low-Power Embedded Systems
   HERCULES
   European Commission
   Horizon 2020 Framework Programme
   688860
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1171918
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