In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10 nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDDlower than 0.4 V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions.

Digital and analog TFET circuits: Design and benchmark / Strangio, S.; Settino, F.; Palestri, P.; Lanuzza, M.; Crupi, F.; Essenia, D.; Selmi, L.. - In: SOLID-STATE ELECTRONICS. - ISSN 0038-1101. - 146:(2018), pp. 50-65. [10.1016/j.sse.2018.05.003]

Digital and analog TFET circuits: Design and benchmark

L. Selmi
2018

Abstract

In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10 nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDDlower than 0.4 V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions.
146
50
65
Digital and analog TFET circuits: Design and benchmark / Strangio, S.; Settino, F.; Palestri, P.; Lanuzza, M.; Crupi, F.; Essenia, D.; Selmi, L.. - In: SOLID-STATE ELECTRONICS. - ISSN 0038-1101. - 146:(2018), pp. 50-65. [10.1016/j.sse.2018.05.003]
Strangio, S.; Settino, F.; Palestri, P.; Lanuzza, M.; Crupi, F.; Essenia, D.; Selmi, L.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1166946
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