We present gate all around strained Si (sSi) nanowire array TFETs with high ION (64μA/μm at VDD=1.0V). Pulsed I-V measurements provide small SS and record I60 of 1×10-2μA/μm at 300K due to the suppression of trap assisted tunneling (TAT). Scaling the nanowires to 10 nm diameter greatly suppresses the impact of TAT and improves SS and ION. Transient analysis of complementary TFET inverters demonstrates experimentally for the first time that device scaling and improved electrostatics yields to faster time response.

Demonstration of Improved Transient Response of Inverters with Steep Slope Strained Si NW TFETs by Reduction of TAT with Pulsed I-V and NW Scaling / L., Knoll; Q. T., Zhao; A., Nichau; S., Richter; G. V., Luong; S., Trellenkamp; A., Schäfer; Selmi, Luca; K. K., Bourdelle; S., Mantl. - STAMPA. - (2013), pp. 4.4.1-4.4.4. (Intervento presentato al convegno 2013 IEEE International Electron Devices Meeting, IEDM 2013 tenutosi a San Francisco, USA nel 9-11 Dicembre 2013) [10.1109/IEDM.2013.6724560].

Demonstration of Improved Transient Response of Inverters with Steep Slope Strained Si NW TFETs by Reduction of TAT with Pulsed I-V and NW Scaling

SELMI, Luca;
2013

Abstract

We present gate all around strained Si (sSi) nanowire array TFETs with high ION (64μA/μm at VDD=1.0V). Pulsed I-V measurements provide small SS and record I60 of 1×10-2μA/μm at 300K due to the suppression of trap assisted tunneling (TAT). Scaling the nanowires to 10 nm diameter greatly suppresses the impact of TAT and improves SS and ION. Transient analysis of complementary TFET inverters demonstrates experimentally for the first time that device scaling and improved electrostatics yields to faster time response.
2013
2013 IEEE International Electron Devices Meeting, IEDM 2013
San Francisco, USA
9-11 Dicembre 2013
4.4.1
4.4.4
L., Knoll; Q. T., Zhao; A., Nichau; S., Richter; G. V., Luong; S., Trellenkamp; A., Schäfer; Selmi, Luca; K. K., Bourdelle; S., Mantl
Demonstration of Improved Transient Response of Inverters with Steep Slope Strained Si NW TFETs by Reduction of TAT with Pulsed I-V and NW Scaling / L., Knoll; Q. T., Zhao; A., Nichau; S., Richter; G. V., Luong; S., Trellenkamp; A., Schäfer; Selmi, Luca; K. K., Bourdelle; S., Mantl. - STAMPA. - (2013), pp. 4.4.1-4.4.4. (Intervento presentato al convegno 2013 IEEE International Electron Devices Meeting, IEDM 2013 tenutosi a San Francisco, USA nel 9-11 Dicembre 2013) [10.1109/IEDM.2013.6724560].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1163520
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