Using state-of-the-art simulation tools ranging from semi-classical Monte-Carlo to full-quantum atomistic approaches, the competitiveness of III-V compounds for next-generation high-performance logic switches is confirmed. A planar double-gate ultra-thinbody (DG-UTB), a triple-gate FinFET, and a gate-allaround nanowire (NW) transistor have been designed according to the ITRS specifications for two technology nodes with physical gate lengths of LG=15 nm and 10.4nm. A thorough performance comparison of digital and analog figures of merit at these nodes reveals that for LG=15 nm, the performance of planar and 3-D architectures is comparable. At LG=10.4 nm, the III-V NW promises the highest performance, especially when lowering the supply voltage from 0.59 V to 0.50 V. It also significantly outperforms its strained silicon counterpart. Finally, the effects of series resistance combined with interface traps, surface roughness, alloy scattering, and electron-phonon interactions have been found to deteriorate the III-V ballistic ON-current by 50-60%.

Performance Projection of III-V Ultra-Thin-Body, FinFET, and Nanowire MOSFETs for two Next-Generation Technology Nodes / Rau, M.; Caruso, Enrico; Lizzit, D.; Palestri, Pierpaolo; Esseni, David; Schenk, A.; Selmi, Luca; Luisier, M.. - ELETTRONICO. - (2017). ((Intervento presentato al convegno 2016 IEEE International Electron Devices Meeting (IEDM) tenutosi a San Francisco nel 3-7 Dec.2016 [10.1109/IEDM.2016.7838515].

Performance Projection of III-V Ultra-Thin-Body, FinFET, and Nanowire MOSFETs for two Next-Generation Technology Nodes

SELMI, Luca;
2017

Abstract

Using state-of-the-art simulation tools ranging from semi-classical Monte-Carlo to full-quantum atomistic approaches, the competitiveness of III-V compounds for next-generation high-performance logic switches is confirmed. A planar double-gate ultra-thinbody (DG-UTB), a triple-gate FinFET, and a gate-allaround nanowire (NW) transistor have been designed according to the ITRS specifications for two technology nodes with physical gate lengths of LG=15 nm and 10.4nm. A thorough performance comparison of digital and analog figures of merit at these nodes reveals that for LG=15 nm, the performance of planar and 3-D architectures is comparable. At LG=10.4 nm, the III-V NW promises the highest performance, especially when lowering the supply voltage from 0.59 V to 0.50 V. It also significantly outperforms its strained silicon counterpart. Finally, the effects of series resistance combined with interface traps, surface roughness, alloy scattering, and electron-phonon interactions have been found to deteriorate the III-V ballistic ON-current by 50-60%.
2016
2016 IEEE International Electron Devices Meeting (IEDM)
San Francisco
3-7 Dec.2016
Rau, M.; Caruso, Enrico; Lizzit, D.; Palestri, Pierpaolo; Esseni, David; Schenk, A.; Selmi, Luca; Luisier, M.
Performance Projection of III-V Ultra-Thin-Body, FinFET, and Nanowire MOSFETs for two Next-Generation Technology Nodes / Rau, M.; Caruso, Enrico; Lizzit, D.; Palestri, Pierpaolo; Esseni, David; Schenk, A.; Selmi, Luca; Luisier, M.. - ELETTRONICO. - (2017). ((Intervento presentato al convegno 2016 IEEE International Electron Devices Meeting (IEDM) tenutosi a San Francisco nel 3-7 Dec.2016 [10.1109/IEDM.2016.7838515].
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11380/1163464
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