In this work, the effect of digital CMOS technology down scaling on the performances of MOS Current Mode Logic frequency dividers is addressed. A fast and effective methodology to design the dividers is presented. The insight given by the methodology is then exploited to study the down scaling of MCML dividers by considering two CMOS technologies representative of the 130 nm and 90 nm technology nodes. The model provides quantitatively accurate predictions of the advantages of scaling on current consumption and maximum frequency of operation.

A Model to Understand Current Consumption, Maximum Operating Frequency And Scaling Trends Of MCML Frequency Dividers / Nonis, Roberto; Palumbo, Enzo; Palestri, Pierpaolo; Selmi, Luca. - (2005), pp. 57-60. ((Intervento presentato al convegno Austrochip 2005 tenutosi a N/A nel october 2005.

A Model to Understand Current Consumption, Maximum Operating Frequency And Scaling Trends Of MCML Frequency Dividers

SELMI, Luca
2005

Abstract

In this work, the effect of digital CMOS technology down scaling on the performances of MOS Current Mode Logic frequency dividers is addressed. A fast and effective methodology to design the dividers is presented. The insight given by the methodology is then exploited to study the down scaling of MCML dividers by considering two CMOS technologies representative of the 130 nm and 90 nm technology nodes. The model provides quantitatively accurate predictions of the advantages of scaling on current consumption and maximum frequency of operation.
Austrochip 2005
N/A
october 2005
57
60
Nonis, Roberto; Palumbo, Enzo; Palestri, Pierpaolo; Selmi, Luca
A Model to Understand Current Consumption, Maximum Operating Frequency And Scaling Trends Of MCML Frequency Dividers / Nonis, Roberto; Palumbo, Enzo; Palestri, Pierpaolo; Selmi, Luca. - (2005), pp. 57-60. ((Intervento presentato al convegno Austrochip 2005 tenutosi a N/A nel october 2005.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11380/1163462
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