This paper presents a novel hysteresis phenomenon induced in the latch-up I-V characteristics of CMOS structures by three dimensional effects producing strongly bias dependent non-uniformities in the current lateral distribution. This behavior has been experimentally reproduced in a lumped element circuit, and a suitable model is presented.
Three dimensional distribution of latch-up current in scaled CMOS structures / Selmi, Luca; Venturi, F; Sangiorgi, Enrico; Ricco, B.. - STAMPA. - (1987), pp. 783-786. (Intervento presentato al convegno 17th European Solid State Device Research Conference, ESSDERC 1987 tenutosi a Bologna (Italia) nel 1987).
Three dimensional distribution of latch-up current in scaled CMOS structures
SELMI, Luca;
1987
Abstract
This paper presents a novel hysteresis phenomenon induced in the latch-up I-V characteristics of CMOS structures by three dimensional effects producing strongly bias dependent non-uniformities in the current lateral distribution. This behavior has been experimentally reproduced in a lumped element circuit, and a suitable model is presented.File | Dimensione | Formato | |
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