This paper presents a benchmark of a virtual III-V TFET nanowire technology platform against the predictive models of CMOS FinFETs for the 10-nm technology node. The standard 28T full adder and the 32-bits ripple carry adder are used as vehicle circuit/architecture for the comparison, respectively. Figures-ofmerit including delays, energy and energy-delay plots are discussed
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS technology node considering 28T Full-Adders / Strangio, Sebastiano; Palestri, Pierpaolo; Lanuzza, M.; Esseni, David; Crupi, F.; Selmi, Luca. - ELETTRONICO. - (2016), pp. 139-142. (Intervento presentato al convegno 2nd Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2016 tenutosi a Vienna, Austria nel 25-27 Jan. 2016) [10.1109/ULIS.2016.7440072].
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS technology node considering 28T Full-Adders
PALESTRI, Pierpaolo;SELMI, Luca
2016
Abstract
This paper presents a benchmark of a virtual III-V TFET nanowire technology platform against the predictive models of CMOS FinFETs for the 10-nm technology node. The standard 28T full adder and the 32-bits ripple carry adder are used as vehicle circuit/architecture for the comparison, respectively. Figures-ofmerit including delays, energy and energy-delay plots are discussed
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