The on-current and its ballistic limit for MOSFETs designed according to the 2003 International Technology Roadmap for Semiconductors down to the 45-nm node, are evaluated by using the full-band, self-consistent Monte Carlo simulator with quantum–mechanical corrections described in Part I. Our results show that quasi-ballistic transport increases for G below approximately 50 nm and contributes most part of the ON improvements related to scaling. Thanks to a lower vertical electric field, double-gate silicon-on-insulator MOSFETs with ultrathin body and low channel doping achieve performance closer to the ballistic limit than the bulk counterparts.
Understanding Quasi-Ballistic Transport in nano-MOSFETs. Part II: Technology Scaling along the ITRS / Eminente, S.; Esseni, David; Palestri, Pierpaolo; Fiegna, C; Selmi, Luca; Sangiorgi, E.. - In: IEEE TRANSACTIONS ON ELECTRON DEVICES. - ISSN 0018-9383. - 52:12(2005), pp. 2736-2743. [10.1109/TED.2005.859566]
Understanding Quasi-Ballistic Transport in nano-MOSFETs. Part II: Technology Scaling along the ITRS
SELMI, Luca;
2005-01-01
Abstract
The on-current and its ballistic limit for MOSFETs designed according to the 2003 International Technology Roadmap for Semiconductors down to the 45-nm node, are evaluated by using the full-band, self-consistent Monte Carlo simulator with quantum–mechanical corrections described in Part I. Our results show that quasi-ballistic transport increases for G below approximately 50 nm and contributes most part of the ON improvements related to scaling. Thanks to a lower vertical electric field, double-gate silicon-on-insulator MOSFETs with ultrathin body and low channel doping achieve performance closer to the ballistic limit than the bulk counterparts.
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