In this work, a benchmark for low-power digital applications of a III-V TFET technology platform against a conventional CMOS FinFET technology node is proposed. The analysis focuses on full-adder circuits, which are commonly identified as representative of the digital logic environment. 28T and 24T topologies, implemented in complementary-logic and transmission-gate logic, respectively, are investigated. Transient simulations are performed with a purpose-built test-bench on each single-bit full adder solution. The extracted delays and energy characteristics are post-processed and translated into figures-of-merit for multi-bit ripple-carry-adders. Trends related to the different full-adder implementations (for the same device technology platform) and to the different technology platforms (for the same full-adder topology) are presented and discussed.
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits / Strangio, Sebastiano; Palestri, Pierpaolo; Lanuzza, M.; Esseni, David; Crupi, F.; Selmi, Luca. - In: SOLID-STATE ELECTRONICS. - ISSN 0038-1101. - STAMPA. - 128:(2017), pp. 37-42. [10.1016/j.sse.2016.10.022]
Benchmarks of a III-V TFET technology platform against the 10-nm CMOS FinFET technology node considering basic arithmetic circuits
PALESTRI, Pierpaolo;SELMI, Luca
2017
Abstract
In this work, a benchmark for low-power digital applications of a III-V TFET technology platform against a conventional CMOS FinFET technology node is proposed. The analysis focuses on full-adder circuits, which are commonly identified as representative of the digital logic environment. 28T and 24T topologies, implemented in complementary-logic and transmission-gate logic, respectively, are investigated. Transient simulations are performed with a purpose-built test-bench on each single-bit full adder solution. The extracted delays and energy characteristics are post-processed and translated into figures-of-merit for multi-bit ripple-carry-adders. Trends related to the different full-adder implementations (for the same device technology platform) and to the different technology platforms (for the same full-adder topology) are presented and discussed.
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