This paper describes the modeling, design, and characterization of a low-jitter 2.4-GHz LC-VCO PLL architecture realized in a standard 0.12-mu m CMOS technology. It features an analog dual control loop for fine and coarse VCO tuning that allows very low VCO gain (60 MHz/V) for noise rejection while maintaining a wide tuning range. The coarse input of the VCO is driven by an analog circuit that adjusts the VCO gain in a continuous manner. Measurements demonstrate an integrated jitter of 0.74 ps that is 43% lower compared to results from a standard PLL topology (STD PLL) with a single control loop. The PLLs have the same bandwidth and output frequency range and were built on the same wafer for comparison. The circuit area of the proposed LC-VCO PLL is 0.7 mm(2) and the power consumption is 32 mW. The area and power consumption of the proposed LC-VCO PLL are less than 1% larger compared to the STD PLL.

Modeling, design and characterization of a new Low Jitter analog Dual Tuning LC-VCO PLL Architecture / Nonis, Roberto; DA DALT, N; Palestri, Pierpaolo; Selmi, Luca. - In: IEEE JOURNAL OF SOLID-STATE CIRCUITS. - ISSN 0018-9200. - 40:6(2005), pp. 1303-1309. [10.1109/JSSC.2005.848037]

Modeling, design and characterization of a new Low Jitter analog Dual Tuning LC-VCO PLL Architecture

PALESTRI, Pierpaolo;SELMI, Luca
2005

Abstract

This paper describes the modeling, design, and characterization of a low-jitter 2.4-GHz LC-VCO PLL architecture realized in a standard 0.12-mu m CMOS technology. It features an analog dual control loop for fine and coarse VCO tuning that allows very low VCO gain (60 MHz/V) for noise rejection while maintaining a wide tuning range. The coarse input of the VCO is driven by an analog circuit that adjusts the VCO gain in a continuous manner. Measurements demonstrate an integrated jitter of 0.74 ps that is 43% lower compared to results from a standard PLL topology (STD PLL) with a single control loop. The PLLs have the same bandwidth and output frequency range and were built on the same wafer for comparison. The circuit area of the proposed LC-VCO PLL is 0.7 mm(2) and the power consumption is 32 mW. The area and power consumption of the proposed LC-VCO PLL are less than 1% larger compared to the STD PLL.
2005
40
6
1303
1309
Modeling, design and characterization of a new Low Jitter analog Dual Tuning LC-VCO PLL Architecture / Nonis, Roberto; DA DALT, N; Palestri, Pierpaolo; Selmi, Luca. - In: IEEE JOURNAL OF SOLID-STATE CIRCUITS. - ISSN 0018-9200. - 40:6(2005), pp. 1303-1309. [10.1109/JSSC.2005.848037]
Nonis, Roberto; DA DALT, N; Palestri, Pierpaolo; Selmi, Luca
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1163056
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