This paper analyzes the potentials and the limitations of a novel LC-Oscillator topology featuring independent gate biasing. The topic is addressed from an experimental perspective. The novel topology has been implemented in a state-of-the-art 32 nm CMOS technology and used as a proof-of-concept. The performance of the oscillator has been evaluated in terms of power consumption and phase-noise. The independent gate biasing helps in relaxing the noise/power trade-off that limits the performance of conventional LC-Oscillators.
LC-Oscillator featuring independent Gate biasing implemented in 32 nm CMOS technology / Ponton, Davide; Palestri, Pierpaolo; Knoblinger, G; Fulde, M; Selmi, Luca. - (2010), pp. 184-187. (Intervento presentato al convegno 2010 International Conference on Microelectronics, ICM'10 tenutosi a Cairo, egy nel 2010) [10.1109/ICM.2010.5696111].
LC-Oscillator featuring independent Gate biasing implemented in 32 nm CMOS technology
PALESTRI, Pierpaolo;SELMI, Luca
2010
Abstract
This paper analyzes the potentials and the limitations of a novel LC-Oscillator topology featuring independent gate biasing. The topic is addressed from an experimental perspective. The novel topology has been implemented in a state-of-the-art 32 nm CMOS technology and used as a proof-of-concept. The performance of the oscillator has been evaluated in terms of power consumption and phase-noise. The independent gate biasing helps in relaxing the noise/power trade-off that limits the performance of conventional LC-Oscillators.
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