In this paper, FinFET stacks consisting of mixed three- (3T) and four-terminal (4T) devices are analyzed in terms of leakage. A novel figure of merit is introduced, and closed-form leakage models are derived. Analytical results are used to derive simple design criteria to minimize the leakage by properly mixing 3T and 4T devices in transistor stacks. The comparison with a bulk technology shows that properly designed FinFET circuits are able to reduce the leakage by one or two orders of magnitude.
Design and evaluation of mixed 3T-4T FinFET stacks for leakage reduction / Agostinelli, M; Alioto, M; Esseni, David; Selmi, Luca. - (2009), pp. 31-41. (Intervento presentato al convegno International Workshop on Power And Timing Modeling, Optimization and Simulation (PATMOS) tenutosi a Lisboa (Portogallo) nel settembre) [10.1007/978-3-540-95948-9_4].
Design and evaluation of mixed 3T-4T FinFET stacks for leakage reduction
SELMI, Luca
2009-01-01
Abstract
In this paper, FinFET stacks consisting of mixed three- (3T) and four-terminal (4T) devices are analyzed in terms of leakage. A novel figure of merit is introduced, and closed-form leakage models are derived. Analytical results are used to derive simple design criteria to minimize the leakage by properly mixing 3T and 4T devices in transistor stacks. The comparison with a bulk technology shows that properly designed FinFET circuits are able to reduce the leakage by one or two orders of magnitude.
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