In CMOS technologies, rapidly becoming the most important ones for VLSI microelectronics, the inherent phenomenon of latch-up, represents one of the most serious limitations for further dimension scaling in the deep sub-micron range. For this reason latch-up has attracted a lot of attention in the last decade and a deep understanding of its essential features has been achieved, although a few specific problems are still to be satisfactorily solved.
Latch-up in CMOS circuits: a review / Sangiorgi, Enrico; Fiegna, C; Menozzi, R; Selmi, Luca; Ricco, B.. - In: TRANSACTIONS ON EMERGING TELECOMMUNICATIONS TECHNOLOGIES. - ISSN 2161-3915. - STAMPA. - 1:3(1990), pp. 107-111. [10.1002/ett.4460010316]
Latch-up in CMOS circuits: a review
SELMI, Luca;
1990
Abstract
In CMOS technologies, rapidly becoming the most important ones for VLSI microelectronics, the inherent phenomenon of latch-up, represents one of the most serious limitations for further dimension scaling in the deep sub-micron range. For this reason latch-up has attracted a lot of attention in the last decade and a deep understanding of its essential features has been achieved, although a few specific problems are still to be satisfactorily solved.
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1990_05_European_T_Telecom_Sangiorgi_Latch-up 2.pdf
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