This work investigates the strain engineering in InAs nanowire Tunnel-FETs. To this purpose we developed a simulator based on the NEGF formalism and employing an 8×8 k·p Hamiltonian. The model accounts for arbitrary crystal orientations and describes the strain implicitly by a modification of the bandstructure. Elastic and inelastic phonon scattering is also accounted for in the self-consistent Born approximation. Our results show that appropriate strain conditions in InAs Tunnel- FETs enable: (a) a remarkable enhancement of the Ion with no significant degradation of the subthreshold slope (SS); (b) large improvements in the Ioff versus Ion tradeoff for low Ioff and VDD values; (c) significant widening of Ioff and VDD window where Tunnel-FETs can compete with silicon MOSFETs.
A simulation study of strain induced performance enhancements in InAs nanowire Tunnel-FETs / Conzatti, F., M. G., P., Esseni, D., E., B., Selmi, L.. - (2011), pp. 5.2.4-5.2.4. (2011 IEEE International Electron Devices Meeting, IEDM 2011 Washington, DC, usa 2011) [10.1109/IEDM.2011.6131492].
A simulation study of strain induced performance enhancements in InAs nanowire Tunnel-FETs
SELMI, Luca
2011
Abstract
This work investigates the strain engineering in InAs nanowire Tunnel-FETs. To this purpose we developed a simulator based on the NEGF formalism and employing an 8×8 k·p Hamiltonian. The model accounts for arbitrary crystal orientations and describes the strain implicitly by a modification of the bandstructure. Elastic and inelastic phonon scattering is also accounted for in the self-consistent Born approximation. Our results show that appropriate strain conditions in InAs Tunnel- FETs enable: (a) a remarkable enhancement of the Ion with no significant degradation of the subthreshold slope (SS); (b) large improvements in the Ioff versus Ion tradeoff for low Ioff and VDD values; (c) significant widening of Ioff and VDD window where Tunnel-FETs can compete with silicon MOSFETs.
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