This paper describes the design of a single-stage differential Low Noise Amplifier (LNA) for Ultra Wide Band(UWB) applications, implemented in state of the art Planar and FinFET 45nm CMOS technologies. A gm-boosted topology has been chosen and the LNA has been designed to work over the whole UWB band (3.1 – 10.6GHz), while driving a capacitive load. The simulations highlight that, at the present stage of the technology development, the Planar version of the LNA outperforms the FinFET one thanks to the superior cutoff frequency fT of Planar devices in the inversion region, achieving comparable Noise Figure and voltage gain, but consuming less power.

Design of UWB LNA in 45nm CMOS Technology: Planar Bulk vs. FinFET / D., Ponton; Palestri, Pierpaolo; Esseni, David; Selmi, Luca; M., Tiebout; B., Parvais; G., Knoblinger. - (2008), pp. 2701-2704. (Intervento presentato al convegno 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 tenutosi a Seattle, WA, usa nel Maggio) [10.1109/ISCAS.2008.4542014].

Design of UWB LNA in 45nm CMOS Technology: Planar Bulk vs. FinFET

PALESTRI, Pierpaolo;SELMI, Luca;
2008

Abstract

This paper describes the design of a single-stage differential Low Noise Amplifier (LNA) for Ultra Wide Band(UWB) applications, implemented in state of the art Planar and FinFET 45nm CMOS technologies. A gm-boosted topology has been chosen and the LNA has been designed to work over the whole UWB band (3.1 – 10.6GHz), while driving a capacitive load. The simulations highlight that, at the present stage of the technology development, the Planar version of the LNA outperforms the FinFET one thanks to the superior cutoff frequency fT of Planar devices in the inversion region, achieving comparable Noise Figure and voltage gain, but consuming less power.
2008
2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008
Seattle, WA, usa
Maggio
2701
2704
D., Ponton; Palestri, Pierpaolo; Esseni, David; Selmi, Luca; M., Tiebout; B., Parvais; G., Knoblinger
Design of UWB LNA in 45nm CMOS Technology: Planar Bulk vs. FinFET / D., Ponton; Palestri, Pierpaolo; Esseni, David; Selmi, Luca; M., Tiebout; B., Parvais; G., Knoblinger. - (2008), pp. 2701-2704. (Intervento presentato al convegno 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008 tenutosi a Seattle, WA, usa nel Maggio) [10.1109/ISCAS.2008.4542014].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1162811
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