We propose a new defect characterization technique for high-k dielectric stacks in III-V MOSFETs. This technique allows extracting the defect density from the simulations of the C-V and G-V characteristics at different frequencies. The simulation is performed using a physical distributed compact model, where the trap-assisted capture and emission processes are described in the framework of the multiphonon trap-assisted tunneling theory, including lattice relaxation. The technique, tested on InGaAs MOS devices with different gate-stacks, allows profiling the interfacial and bulk defects in the (E, z) domain. The extracted map, consistent with previous report, allows reproducing C-V and G-V curves on the whole frequency and gate voltage ranges and monitoring the quality of dielectric stacks for the optimization of the manufacturing process.

A New Physical Method Based on CV--GV Simulations for the Characterization of the Interfacial and Bulk Defect Density in High-k/III--V MOSFETs / Sereni, Gabriele; Vandelli, Luca; Veksler, Dmitry; Larcher, Luca. - In: IEEE TRANSACTIONS ON ELECTRON DEVICES. - ISSN 0018-9383. - 62:3(2015), pp. 705-712. [10.1109/TED.2014.2385959]

I metadati presenti in IRIS UNIMORE sono rilasciati con licenza Creative Commons CC0 1.0 Universal, mentre i file delle pubblicazioni sono rilasciati con licenza Attribuzione 4.0 Internazionale (CC BY 4.0), salvo diversa indicazione.
In caso di violazione di copyright, contattare Supporto Iris

Powered by IRIS-about IRIS-Utilizzo dei cookie

 Copyright © 2022