The electrical properties of Ru/SrTiO<inf>x</inf>/Ru capacitors have been investigated. Equivalent Oxide Thickness (EOT) of 0.38 nm at 0 V and current density of 10<sup>-7</sup> A cm<sup>-2</sup> at ±1 V and 25 °C meet the sub-20 nm DRAM requirements. Relaxation measurements were performed, indicating acceptable charge loss. Modeling of charge trapping at defect sites based on multi-phonon trap-assisted-tunneling quantitatively well describes leakage and capacitance behavior.

SrTiO<inf>x</inf> for sub-20 nm DRAM technology nodes - Characterization and modeling / Kaczer, B.; Larcher, Luca; Vandelli, Luca; Reisinger, H.; Popovici, M.; Clima, S.; Ji, Z.; Joshi, S.; Swerts, J.; Redolfi, A.; Afanas'Ev, V. V.; Jurczak, M.. - In: MICROELECTRONIC ENGINEERING. - ISSN 0167-9317. - 147:(2015), pp. 126-129. [10.1016/j.mee.2015.04.070]

SrTiOx for sub-20 nm DRAM technology nodes - Characterization and modeling

LARCHER, Luca;VANDELLI, LUCA;
2015-01-01

Abstract

The electrical properties of Ru/SrTiOx/Ru capacitors have been investigated. Equivalent Oxide Thickness (EOT) of 0.38 nm at 0 V and current density of 10-7 A cm-2 at ±1 V and 25 °C meet the sub-20 nm DRAM requirements. Relaxation measurements were performed, indicating acceptable charge loss. Modeling of charge trapping at defect sites based on multi-phonon trap-assisted-tunneling quantitatively well describes leakage and capacitance behavior.
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SrTiO<inf>x</inf> for sub-20 nm DRAM technology nodes - Characterization and modeling / Kaczer, B.; Larcher, Luca; Vandelli, Luca; Reisinger, H.; Popovici, M.; Clima, S.; Ji, Z.; Joshi, S.; Swerts, J.; Redolfi, A.; Afanas'Ev, V. V.; Jurczak, M.. - In: MICROELECTRONIC ENGINEERING. - ISSN 0167-9317. - 147:(2015), pp. 126-129. [10.1016/j.mee.2015.04.070]
Kaczer, B.; Larcher, Luca; Vandelli, Luca; Reisinger, H.; Popovici, M.; Clima, S.; Ji, Z.; Joshi, S.; Swerts, J.; Redolfi, A.; Afanas'Ev, V. V.; Jurczak, M.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1131116
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