Threshold voltage instabilities in D-mode GaN HEMTs for power switching applications

Threshold voltage instabilities observed in GaN HEMTs designed for power switching applications when submitted to either DC or pulsed testing are here presented and interpreted. Main results can be summarized as follows: i) two acceptor trap levels, characterized by two well distinct time constants, are present in the UID GaN channel and C-doped GaN buffer respectively and behave as electron and hole traps respectively; ii) the trapped charge is modulated by the high voltage biasing of the gate and drain terminals; iii) when empty, channel electron traps induce a negative threshold-voltage shift, while buffer hole traps induce a positive threshold-voltage shift; iv) when the device is pulsed from off-to on-state conditions, trap charge/discharge dynamics induces negative and positive threshold-voltage instabilities over distinct time scales.