The paper investigates the possibility to realize in a low cost 130nm CMOS technology a direct conversion architecture wherethe LNB receives the composite signal from the satellite and provides at the output in one step the I and Q bit stream at the base band. A phase locked loop is investigate to realizethe local oscillator of the receiver. Thetechnology capabilities are investigated for the groundreceiver (e.g. in the DVB-S the down-linkfrequency band is 10.7 – 12.75 GHz) as far as forthe on-satellite receiver (e.g. in the DVB-S the uplink frequency band is 12.9 – 18.4 GHz).
A Phase Noise Performance Study of 15 GHz Phase Locked Loop in 130nm CMOS Technology for DVB-S Application / Magnani, Alessandro; P., Lucchi; T., Parra; G., Jacquemod; Borgarino, Mattia. - ELETTRONICO. - (2012), pp. n.a.-n.a.. (Intervento presentato al convegno Sophia Antipolis Microelectronics Forum tenutosi a Sophia Antipolis (Francia) nel 2-3 ottobre 2012).
A Phase Noise Performance Study of 15 GHz Phase Locked Loop in 130nm CMOS Technology for DVB-S Application
MAGNANI, ALESSANDRO;BORGARINO, Mattia
2012
Abstract
The paper investigates the possibility to realize in a low cost 130nm CMOS technology a direct conversion architecture wherethe LNB receives the composite signal from the satellite and provides at the output in one step the I and Q bit stream at the base band. A phase locked loop is investigate to realizethe local oscillator of the receiver. Thetechnology capabilities are investigated for the groundreceiver (e.g. in the DVB-S the down-linkfrequency band is 10.7 – 12.75 GHz) as far as forthe on-satellite receiver (e.g. in the DVB-S the uplink frequency band is 12.9 – 18.4 GHz).
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