Monte Carlo simulation of charge transport in amorphous chalcogenides

Chalcogenide $mathrm{Ge_2Sb_2Te_5}$ material (GST) can suitably be exploited for manufacturing phase-change memory devices. Crystalline GST exhibits an almost Ohmic I(V) curve. In contrast, the amorphous GST shows a high resistance at low biases while, above a threshold voltage, a transition takes place from a highly resistive to a conductive state, characterized by a swift rise of the current along with a voltage snap back ~cite{Pirovano2004} .A clear and correct understanding of the threshold behavior is of the utmost importance for exploiting GST in the fabrication of innovative nonvolatile memories.Experimental structural information and first-principle studies of amorphous GST suggest that the most appropriate transport picture is the one based on hopping processes through localized states~cite{Mott1961} due to a combination of tunneling and thermal excitation.A trap-conduction model is used in this work, where the current flow is due to electron hopping among donor-type traps.Transitions are accounted for according to the variable-range hopping theory. The electron phonon-assisted transition rate is evaluated according to the rate equation in ~cite{miller1960}, taking into account nonlinear effects in the electric field. The physical model summarized above is used for the first time to evaluate the electrical properties of a nanometric 3D layer of amorphous GST in contact with two metallic electrodes by means of a Monte Carlo simulation.The standard voltage-driven Monte Carlo framework has been modified into a current-driven simulation, which better compares to the typical experimental setup.The numerical procedure includes a self-consistent solution of the electric potential. The latter, in fact, has a strong influence onto the hopping rate.Results show that a realistic theoretical transport framework based on the variable-range hopping yields a complete microscopic description of the mechanism governing the threshold switching. In particular, the snap-back effect is correlated to the formation of domains of opposite charges within the device.egin{thebibliography}{9}ibitem{pirovano2004} A. Pirovano, A. Lacaita, A. Benvenuti, F. Pellizzer, and R. Bez, extit{IEEE Trans. Electron. Devices}, vol.51(3), p.452 (2004).ibitem{Mott1961} N.F. Mott and E.A. Davis, extit{Electronic Processes in Non-Crystalline Materials}, Oxford: Clarendon Press (1961).ibitem{miller1960} A. Miller and E. Abrahams, extit{Phys.

The I(V) characteristics of amorphous GST devices show a peculiar S-shape behavior, that is a swift rise of the current along with a voltage snap-back. This type of characteristics led to a growing research interest in view of the future application of such materials to the manufacturing of phase-change memory devices. In this work we adopt a generalization of the variable-range hopping theory to simulate charge transport in a layer of amorphous Ge 2Sb2Te5 sandwiched between two planar metallic electrodes. The numerical implementation of a current-driven Monte Carlo code allows one both to provide a complete microscopic particle picture of electrical conduction in the device and to better analyze the mechanisms governing the snap-back effect. © 2009 IOP Publishing Ltd.