A harmonic oscillator topology displaying an improved phase noise performance is introduced in this paper. Exploiting the advantages yielded by operating the core transistors in class-C, a theoretical 3.9 dB phase noise improvement compared to the standard differential-pair LC-tank oscillator is achieved for the same current consumption. Further benefits derive from the natural rejection of the tail bias current noise, and from the absence of parasitic nodes sensitive to stray capacitances. Closed-form phase-noise equations obtained from a rigorous time-variant circuit analysis are presented, as well as a time-variant study of the stability of the oscillation amplitude, resulting in simple guidelines for a reliable design. Furthermore, the analysis of phase noise is extended to encompass a general harmonic oscillator, showing that all phase noise relations previously obtained for specific LC oscillator topologies are special cases of a very general and remarkably simple result.Two prototypes of the (voltage-controlled) oscillator are implemented in a standard RF 0.13 m CMOS technology. They are tunable over the frequency bands 4.90-5.65 GHz and 4.50–5.00 GHz, respectively, and display an average phase noise lower than 130 dBc/Hz @ 3 MHz from the carrier with a power consumption of 1.4 mW, for a state-of-the-art figure-of-merit ranging from 193.5 dBc/Hz to 196.0 dBc/Hz.
Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise / Mazzanti, Andrea; P., Andreani. - In: IEEE JOURNAL OF SOLID-STATE CIRCUITS. - ISSN 0018-9200. - STAMPA. - 43:12(2008), pp. 2716-2729. [10.1109/JSSC.2008.2004867]
Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise
MAZZANTI, Andrea;
2008
Abstract
A harmonic oscillator topology displaying an improved phase noise performance is introduced in this paper. Exploiting the advantages yielded by operating the core transistors in class-C, a theoretical 3.9 dB phase noise improvement compared to the standard differential-pair LC-tank oscillator is achieved for the same current consumption. Further benefits derive from the natural rejection of the tail bias current noise, and from the absence of parasitic nodes sensitive to stray capacitances. Closed-form phase-noise equations obtained from a rigorous time-variant circuit analysis are presented, as well as a time-variant study of the stability of the oscillation amplitude, resulting in simple guidelines for a reliable design. Furthermore, the analysis of phase noise is extended to encompass a general harmonic oscillator, showing that all phase noise relations previously obtained for specific LC oscillator topologies are special cases of a very general and remarkably simple result.Two prototypes of the (voltage-controlled) oscillator are implemented in a standard RF 0.13 m CMOS technology. They are tunable over the frequency bands 4.90-5.65 GHz and 4.50–5.00 GHz, respectively, and display an average phase noise lower than 130 dBc/Hz @ 3 MHz from the carrier with a power consumption of 1.4 mW, for a state-of-the-art figure-of-merit ranging from 193.5 dBc/Hz to 196.0 dBc/Hz.Pubblicazioni consigliate
I metadati presenti in IRIS UNIMORE sono rilasciati con licenza Creative Commons CC0 1.0 Universal, mentre i file delle pubblicazioni sono rilasciati con licenza Attribuzione 4.0 Internazionale (CC BY 4.0), salvo diversa indicazione.
In caso di violazione di copyright, contattare Supporto Iris