This research aims to explore possible solutions to improvementof performance in multimedia processor [1]. In this context, cache memory performance plays a more and more critical role in computer systems, since the gap between processor speed and main memory speed tends to increase rather than the contrary. The integration inside the computational units of some SIMD improvements (such as Pentinm MMX, HP MAX2 or UltraSparc VIS) for improving the parallel computation on image pixels is the main answer to the heavy workloads of multimedia applications [2]. Moreover, the workload of multimedia applications [3] has a strong impact on cache memory performance, since the locality of memory references embedded in multimedia programs differs from that of traditional programs. In fact, as widely known, programs exhibit two main kind of locality: spatial and temporal. Nevertheless, as stated in [1],multimedia applications seem to present a new kind of locality,called 2D-spatial locality (i.e. there is an high probability that accessing to an address, future accesses will be in a bidimensional neighborhood of it). For this reason, standard cache memory organization achieves poorer performancewhen used for multimedia. To achieve an overall performance improvement on specialized multimedia processors, further architectural modification on memory hierarchy and on its management should be fulfilled. This could be coupled with the recent idea of associating programmable components with memory separated from the main processor, such as IRAM [4].