This paper shows that CMOS Class-E PAs are capable of high Power-Added Efficiency (PAE), even when delivering large output powers at Radio Frequency (RF). In particular, a cascode device is used to obtain high efficiency while assuring reliable operation. A differential solution has been adopted to maximize 2nd harmonic suppression and minimize potential on-chip interference. Prototypes realized in 0.13μm CMOS technology using thick oxide devices show the following performances: 31dBm maximum output power at 1.7GHz with 67% drain efficiency and 58% PAE, -51dBc and -39.5dBc suppression for 2nd and 3rd harmonics, respectively.
This paper shows that CMOS Class-E PAs are capable of high Power-Added Efficiency (PAE), even when delivering large output powers at Radio Frequency (RF). In particular, a cascode device is used to obtain high efficiency while assuring reliable operation. A differential solution has been adopted to maximize 2nd harmonic suppression and minimize potential on-chip interference. Prototypes realized in 0.13mu;m CMOS technology using thick oxide devices show the following performances: 31dBm maximum output power at 1.7GHz with 67% drain efficiency and 58% PAE, -51dBc and -39.5dBc suppression for 2nd and 3rd harmonics, respectively.
A 1.7GHz 31dBm differential CMOS Class-E Power Amplifier with 58% PAE / Brama, Riccardo; Larcher, Luca; Mazzanti, Andrea; F., Svelto. - STAMPA. - (2007), pp. 551-554. (Intervento presentato al convegno 29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 tenutosi a San José (California) nel Settembre 2007) [10.1109/CICC.2007.4405792].
A 1.7GHz 31dBm differential CMOS Class-E Power Amplifier with 58% PAE
BRAMA, Riccardo;LARCHER, Luca;MAZZANTI, Andrea;
2007
Abstract
This paper shows that CMOS Class-E PAs are capable of high Power-Added Efficiency (PAE), even when delivering large output powers at Radio Frequency (RF). In particular, a cascode device is used to obtain high efficiency while assuring reliable operation. A differential solution has been adopted to maximize 2nd harmonic suppression and minimize potential on-chip interference. Prototypes realized in 0.13mu;m CMOS technology using thick oxide devices show the following performances: 31dBm maximum output power at 1.7GHz with 67% drain efficiency and 58% PAE, -51dBc and -39.5dBc suppression for 2nd and 3rd harmonics, respectively.
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