Plasma treatments, indispensable for manufacturing of ULSI integrated circuits, may lead to a latent damage in gate oxides of CMOS components. Latent damage may endanger the device long-term reliability, which is usually tested over large area MOS devices. In this work, we investigated the impact of latent plasma induced damage on the reliability of nMOSFETs with small gate area and gate oxide thickness of 3.2 nm. To this purpose, we stressed 1,500 devices with different antenna areas by using a staircase-like stress voltage, and by monitoring the gate leakage at the gate voltage VG=2V. The stress was always stopped because of an abrupt jump in the gate current. The statistics obtained for the breakdown current is characterized by two different oxide breakdown modes. The first is the well-known HardBreakdown, while the second one, which we called Micro Breakdown, can be modeled as a Double Trap Assisted Tunneling mechanism, and is characterized by a very small leakage current (around 100pA at the gate voltage VG=2V). In devices with large antenna, i.e., more prone to be damaged by plasma processing, the number of micro broken oxides is larger and breakdown occurs at lower voltages than in reference devices (non plasma damaged). For converse, the Hard Breakdown statistics shows only a weak dependence on the gate antenna ratio of plasma damaged devices. This has been explained by considering the intrinsic nature of latent plasma-induced oxide defects, linkedto the different generation mechanisms involved in Micro Breakdown and Hard Breakdown phenomena.

Plasma-induced Micro Breakdown in small area MOSFETs / G., Cellere; Larcher, Luca; M. G., Valentini; A., Paccagnella. - In: IEEE TRANSACTIONS ON ELECTRON DEVICES. - ISSN 0018-9383. - STAMPA. - 49:10(2002), pp. 1768-1774. [10.1109/TED.2002.803637]

Plasma-induced Micro Breakdown in small area MOSFETs

LARCHER, Luca;
2002

Abstract

Plasma treatments, indispensable for manufacturing of ULSI integrated circuits, may lead to a latent damage in gate oxides of CMOS components. Latent damage may endanger the device long-term reliability, which is usually tested over large area MOS devices. In this work, we investigated the impact of latent plasma induced damage on the reliability of nMOSFETs with small gate area and gate oxide thickness of 3.2 nm. To this purpose, we stressed 1,500 devices with different antenna areas by using a staircase-like stress voltage, and by monitoring the gate leakage at the gate voltage VG=2V. The stress was always stopped because of an abrupt jump in the gate current. The statistics obtained for the breakdown current is characterized by two different oxide breakdown modes. The first is the well-known HardBreakdown, while the second one, which we called Micro Breakdown, can be modeled as a Double Trap Assisted Tunneling mechanism, and is characterized by a very small leakage current (around 100pA at the gate voltage VG=2V). In devices with large antenna, i.e., more prone to be damaged by plasma processing, the number of micro broken oxides is larger and breakdown occurs at lower voltages than in reference devices (non plasma damaged). For converse, the Hard Breakdown statistics shows only a weak dependence on the gate antenna ratio of plasma damaged devices. This has been explained by considering the intrinsic nature of latent plasma-induced oxide defects, linkedto the different generation mechanisms involved in Micro Breakdown and Hard Breakdown phenomena.
2002
49
10
1768
1774
Plasma-induced Micro Breakdown in small area MOSFETs / G., Cellere; Larcher, Luca; M. G., Valentini; A., Paccagnella. - In: IEEE TRANSACTIONS ON ELECTRON DEVICES. - ISSN 0018-9383. - STAMPA. - 49:10(2002), pp. 1768-1774. [10.1109/TED.2002.803637]
G., Cellere; Larcher, Luca; M. G., Valentini; A., Paccagnella
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/454241
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