An extensive characterization of the on-state break-down characteristics of GaAs based MESFETs and HEMTs has been carried out by means of dc and pulsed measurements and of circuit simulations. A computer-controlled, three-terminals Transmission Line Pulse (TLP) system with 50-100 ns pulse width and sub-ns risetime has been developed, which allows automated pulsed measurements of device I-V characteristics. The TLP system has been adopted for nondestructive measurements of the on-state breakdown characteristics of GaAs MESFETs and HEMTs up to unprecedented values of gate current density (IG/W = 30 mA/mm has been reached), in strong avalanche conditions. The device behavior in strong avalanche conditions is dominated by a parasitic bipolar effect (PBE) similarly to SOI and bulk Si MOSFETs. By taking into account this and other parasitic effects, an equivalent circuit model, suitable for SPICE simulations has been developed. The proposed model is capable of predicting the exact behavior of the gate and drain currents in both weak and strong avalanche conditions.
Pulsed measurements and circuit modeling of weak and strong avalanche effects in GaAs MESFETs and HEMTs / Meneghesso, G.; Chini, Alessandro; Maretto, M.; Zanoni, E.. - In: IEEE TRANSACTIONS ON ELECTRON DEVICES. - ISSN 0018-9383. - STAMPA. - 50:2(2003), pp. 324-332. [10.1109/TED.2003.809037]
Pulsed measurements and circuit modeling of weak and strong avalanche effects in GaAs MESFETs and HEMTs
CHINI, Alessandro;
2003
Abstract
An extensive characterization of the on-state break-down characteristics of GaAs based MESFETs and HEMTs has been carried out by means of dc and pulsed measurements and of circuit simulations. A computer-controlled, three-terminals Transmission Line Pulse (TLP) system with 50-100 ns pulse width and sub-ns risetime has been developed, which allows automated pulsed measurements of device I-V characteristics. The TLP system has been adopted for nondestructive measurements of the on-state breakdown characteristics of GaAs MESFETs and HEMTs up to unprecedented values of gate current density (IG/W = 30 mA/mm has been reached), in strong avalanche conditions. The device behavior in strong avalanche conditions is dominated by a parasitic bipolar effect (PBE) similarly to SOI and bulk Si MOSFETs. By taking into account this and other parasitic effects, an equivalent circuit model, suitable for SPICE simulations has been developed. The proposed model is capable of predicting the exact behavior of the gate and drain currents in both weak and strong avalanche conditions.
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