Purpose of this work was to study the gate oxide leakage current in small area MOSFETs. We stressed about 300 nMOSFETs with an oxide thickness tOX=3.2 nm by using a staircase gate voltage. We detected the oxide breakdown at an early stress stage, by measuring the leakage current at low fields during the stress. The gate leakage of stressed devices is broadly distributed, but two well-defined current regimes appear, corresponding to currents larger than 1mA or smaller than 100pA, respectively. We focused our attention on the small current regime, which shows all the electrical characteristics typical of the soft breakdown, with the noticeable exception of the current intensity that is much smaller than usually reported in literature, being the average leakage around 40pA at VG=+2V. For this reason, we introduce the oxide micro breakdown. The leakage kinetics during stress, the gate-voltage characteristics of stressed devices, and the breakdown statistical distributions are in agreement with the formation of a single conductive path across the oxide formed by few oxide defects. Just two positively charged traps can give rise to a gate leakage comparable to those experimentally found, as evaluated by using an new original model of Double Trap Assisted Tunneling (D-TAT) developed ad hoc.
|Anno di pubblicazione:||2002|
|Titolo:||Micro breakdown in small-area ultra-thin gate oxide|
|Autore/i:||Cellere G.; Larcher L.; Valentini M G.; Paccagnella A.|
|Codice identificativo Scopus:||2-s2.0-0036685471|
|Tipologia||Articolo su rivista|
File in questo prodotto:
I documenti presenti in Iris Unimore sono rilasciati con licenza Creative Commons Attribuzione - Non commerciale - Non opere derivate 3.0 Italia, salvo diversa indicazione.
In caso di violazione di copyright, contattare Supporto Iris