Analytical expressions for the thermal resistance of bipolar transistors on bulk and SOI substrates are presented. The models are derived on the basis of intuitive physical pictures and validated by comparison with experimental data and three-dimensional (3D) device simulation. The effect of bulk and SOI substrates, shallow- and deep-trench isolation, and multiple emitter fingers is accounted for. All models are suitable for both hand calculations and computer-aided design.
Compact Modeling of Thermal Resistance in Bipolar Transistors on Bulk and SOI substrates / Pacelli, A.; Palestri, Pierpaolo; Mastrapasqua, M.. - In: IEEE TRANSACTIONS ON ELECTRON DEVICES. - ISSN 0018-9383. - 49:6(2002), pp. 1027-1033. [10.1109/TED.2002.1003724]
Compact Modeling of Thermal Resistance in Bipolar Transistors on Bulk and SOI substrates
PALESTRI, Pierpaolo;
2002
Abstract
Analytical expressions for the thermal resistance of bipolar transistors on bulk and SOI substrates are presented. The models are derived on the basis of intuitive physical pictures and validated by comparison with experimental data and three-dimensional (3D) device simulation. The effect of bulk and SOI substrates, shallow- and deep-trench isolation, and multiple emitter fingers is accounted for. All models are suitable for both hand calculations and computer-aided design.
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