This paper analyzes the scaling of LC voltage controlled oscillator (LC-VCO) implemented in advanced planar CMOS technologies. An LC-VCO for GSM applications, has been designed in state-of-the-art 45/40 nm and 32 nm CMOS technologies, exploiting different front- and back-end of line (FEOL/BEOL) options. The designs are compared with each other and with recent literature in terms of power and phase-noise performance.

Assessment of the impact of technology scaling on the performance of LC-VCOs / Ponton, Davide; Knoblinger, G; Roithmeier, A; Tiebout, M; Fulde, M; Palestri, Pierpaolo. - (2009), pp. 351-367. (Intervento presentato al convegno Proceedings IEEE Solid-State Circuits Conference (ESSCIRC) tenutosi a Atene (GR), 14-18 settembre 2009 nel settembre) [10.1109/ESSDERC.2009.5331398].

Assessment of the impact of technology scaling on the performance of LC-VCOs

PALESTRI, Pierpaolo
2009

Abstract

This paper analyzes the scaling of LC voltage controlled oscillator (LC-VCO) implemented in advanced planar CMOS technologies. An LC-VCO for GSM applications, has been designed in state-of-the-art 45/40 nm and 32 nm CMOS technologies, exploiting different front- and back-end of line (FEOL/BEOL) options. The designs are compared with each other and with recent literature in terms of power and phase-noise performance.
2009
Proceedings IEEE Solid-State Circuits Conference (ESSCIRC)
Atene (GR), 14-18 settembre 2009
settembre
351
367
Ponton, Davide; Knoblinger, G; Roithmeier, A; Tiebout, M; Fulde, M; Palestri, Pierpaolo
Assessment of the impact of technology scaling on the performance of LC-VCOs / Ponton, Davide; Knoblinger, G; Roithmeier, A; Tiebout, M; Fulde, M; Palestri, Pierpaolo. - (2009), pp. 351-367. (Intervento presentato al convegno Proceedings IEEE Solid-State Circuits Conference (ESSCIRC) tenutosi a Atene (GR), 14-18 settembre 2009 nel settembre) [10.1109/ESSDERC.2009.5331398].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1328065
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