The embedded NOR-type Non Volatile Memory (eNVM) cell is characterized by many figures of merit. Of particular interest are the programming efficiency (PE), defined as the electron gate-to-drain current ratio (Ig/Id) during programming, and the drain disturb current (DDC), defined as the hole gate current Igh during drain disturb (Fig. 1). eNVM gate-length scaling has brought shallower and steeper Source/Drain (S/D) junctions enabling not only higher PE but also increased DDC, the latter yielding to potential reliability issues. Therefore, in the spirit of a compromise in channel/LDD implant conditions is here presented, showing a trade-off between electron and hole injection during programming and drain disturb phases, respectively.
Programming Efficiency and Drain Disturb Trade-Off in Embedded Non Volatile Memories / A., Zaka; Palestri, Pierpaolo; D., Rideau; Iellina, Matteo; E., Dormel; Q., Rafhay; C., Tavernier; H., Jaouen. - (2010), pp. 323-326. (Intervento presentato al convegno 2010 14th International Workshop on Computational Electronics, IWCE 2010 tenutosi a Pisa, ita nel Ottobre) [10.1109/IWCE.2010.5677949].
Programming Efficiency and Drain Disturb Trade-Off in Embedded Non Volatile Memories
PALESTRI, Pierpaolo;
2010
Abstract
The embedded NOR-type Non Volatile Memory (eNVM) cell is characterized by many figures of merit. Of particular interest are the programming efficiency (PE), defined as the electron gate-to-drain current ratio (Ig/Id) during programming, and the drain disturb current (DDC), defined as the hole gate current Igh during drain disturb (Fig. 1). eNVM gate-length scaling has brought shallower and steeper Source/Drain (S/D) junctions enabling not only higher PE but also increased DDC, the latter yielding to potential reliability issues. Therefore, in the spirit of a compromise in channel/LDD implant conditions is here presented, showing a trade-off between electron and hole injection during programming and drain disturb phases, respectively.
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