This work describes the design of a transmitter for a 10 Gbps serial interface to be used in automotive Electronic Control Units. The data rate is chosen in order to assess the design challenges in automotive environment at this frequency. The focus will be mainly on challenges related to transistor level design using a standard 28 nm technology, nevertheless a system level overview will be also given. The proposed transmitter features feed-forward equalization with 8 taps (1 pre-cursor and 6 postcursors, plus the main tap), whose strength is programmable with 16 discretization steps, optimizing the transmitter adaptability with reduced area. The proposed architecture is also able to tune its output impedance independently from the choice of the weights of the equalization tap. It features a 300 mV peak-topeak eye diagram with 16 equalization levels and achieves a remarkably low 2.25 pJ/bit total power consumption (0.633 pJ/bit for the predriver+driver).
Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers / Bandiziol, A., Grollitsch, W., Brandonisio, F., Nonis, R., Palestri, P.. - (2017), pp. 321-324. (2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016 Jeju, Korea (South) October 25, 2016 to October 28, 2016) [10.1109/APCCAS.2016.7803964].
Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers
PALESTRI, Pierpaolo
2017
Abstract
This work describes the design of a transmitter for a 10 Gbps serial interface to be used in automotive Electronic Control Units. The data rate is chosen in order to assess the design challenges in automotive environment at this frequency. The focus will be mainly on challenges related to transistor level design using a standard 28 nm technology, nevertheless a system level overview will be also given. The proposed transmitter features feed-forward equalization with 8 taps (1 pre-cursor and 6 postcursors, plus the main tap), whose strength is programmable with 16 discretization steps, optimizing the transmitter adaptability with reduced area. The proposed architecture is also able to tune its output impedance independently from the choice of the weights of the equalization tap. It features a 300 mV peak-topeak eye diagram with 16 equalization levels and achieves a remarkably low 2.25 pJ/bit total power consumption (0.633 pJ/bit for the predriver+driver).| File | Dimensione | Formato | |
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