This paper presents the experimental characterization of a High-Speed Serial Interface (HSSI) for automotive microcontroller applications designed in 28 nm planar CMOS technology, verified over automotive corners and operating up to 11 Gb/s. The impedance of the full-rate voltage-mode transmitter can be tuned by activating several driver replicas. It also features an 8-tap Feed-Forward Equalizer (FFE) with taps programmable in steps of 1/16. The analog front-end of the receiver cascades a Variable-Gain Amplifier (VGA) and a Continuous-Time Linear Equalizer (CTLE), which can be individually tuned. The receiver is based on a half-rate architecture and features a 3-tap Decision-Feedback Equalizer (DFE), one tap being speculative to relax timing constraints; another VGA is embedded in the DFE summing node. The subsequent data and edge samplers are offset-compensated. The circuit is experimentally characterized over automotive corners at 6.25 Gb/s and 11 Gb/s on highly-reflecting PCB channels with up to 14.5 dB loss, demonstrating operations at bit-error ratio (BER) below 10 −12 up to 11 Gb/s. The HSSI occupies an area of 0.08 mm 2 and consumes 8.4 mW/Gb/s at 11 Gb/s and 6.2mW/Gb/s at 6.25 Gb/s.
Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers / D'Ampolo, Dylan; Bandiziol, Andrea; Menin, Davide; Grollitsch, Werner; Nonis, Roberto; Palestri, Pierpaolo. - (2019), pp. 225-228. (Intervento presentato al convegno 15th Annual IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2019 tenutosi a Bangkok, THAILAND nel NOV 11-14, 2019) [10.1109/APCCAS47518.2019.8953093].
Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers
Palestri, Pierpaolo
2019
Abstract
This paper presents the experimental characterization of a High-Speed Serial Interface (HSSI) for automotive microcontroller applications designed in 28 nm planar CMOS technology, verified over automotive corners and operating up to 11 Gb/s. The impedance of the full-rate voltage-mode transmitter can be tuned by activating several driver replicas. It also features an 8-tap Feed-Forward Equalizer (FFE) with taps programmable in steps of 1/16. The analog front-end of the receiver cascades a Variable-Gain Amplifier (VGA) and a Continuous-Time Linear Equalizer (CTLE), which can be individually tuned. The receiver is based on a half-rate architecture and features a 3-tap Decision-Feedback Equalizer (DFE), one tap being speculative to relax timing constraints; another VGA is embedded in the DFE summing node. The subsequent data and edge samplers are offset-compensated. The circuit is experimentally characterized over automotive corners at 6.25 Gb/s and 11 Gb/s on highly-reflecting PCB channels with up to 14.5 dB loss, demonstrating operations at bit-error ratio (BER) below 10 −12 up to 11 Gb/s. The HSSI occupies an area of 0.08 mm 2 and consumes 8.4 mW/Gb/s at 11 Gb/s and 6.2mW/Gb/s at 6.25 Gb/s.
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