Half SRAM cells with strained Si nanowire complementary Tunnel-FETs (CTFET) have been fabricated to explore the capability of TFETs for 6T-SRAM. Static measurements on cells with outward faced n-TFET access transistors have been performed to determine the SRAM butterfly curves, allowing the assessment of cell functionality and stability. The forward p-i-n leakage at certain bias configuration of the access transistor may lead to malfunctioning storage operation, even without the contribution of the ambipolar behavior. Lowering the bit-line bias is found to mitigate such effect resulting in functional hold, read and write operation.
Experimental characterization of the Static Noise Margins of strained Silicon complementary Tunnel-FET SRAM / Luong, G. V.; Strangio, Sebastiano; Tiedemann, A. T.; Bernardy, P.; Trellenkamp, S.; Palestri, Pierpaolo; Mantl, S.; Zhao, Q. T.. - (2017), pp. 42-45. (Intervento presentato al convegno 47th European Solid-State Device Research Conference, ESSDERC 2017 tenutosi a bel nel 11-14//09/2017) [10.1109/ESSDERC.2017.8066587].
Experimental characterization of the Static Noise Margins of strained Silicon complementary Tunnel-FET SRAM
PALESTRI, Pierpaolo;
2017
Abstract
Half SRAM cells with strained Si nanowire complementary Tunnel-FETs (CTFET) have been fabricated to explore the capability of TFETs for 6T-SRAM. Static measurements on cells with outward faced n-TFET access transistors have been performed to determine the SRAM butterfly curves, allowing the assessment of cell functionality and stability. The forward p-i-n leakage at certain bias configuration of the access transistor may lead to malfunctioning storage operation, even without the contribution of the ambipolar behavior. Lowering the bit-line bias is found to mitigate such effect resulting in functional hold, read and write operation.
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