Recent commercial hardware platforms for embedded real-time systems feature heterogeneous processing units and computing accelerators on the same System-on-Chip. When designing complex real-time applications for such architectures, the designer is exposed to a number of difficult choices, like deciding on which compute engine to execute a certain task, or what degree of parallelism to adopt for a given function. To help the designer exploring the wide space of design choices and tune the scheduling parameters, we propose a novel real-time application model, called HPC-DAG (Heterogeneous Parallel Condition Directed Acyclic Graph Model), specifically conceived for heterogeneous platforms. An HPC-DAG allows the system designer to specify alternative implementations of a software component for different processing engines, as well as conditional branches to model if-then-else statements. We also propose a schedulability analysis for the HPC-DAG model and a set of heuristic allocation algorithms aimed at improving schedulability for latency sensitive applications. Our analysis takes into account the cost of preempting a task, which can be non-negligible on certain processors. We show the use of our approach on a realistic case study, and we demonstrate its effectiveness by comparing it with state-of-the-art algorithms previously proposed in literature.

The HPC-DAG Task Model for Heterogeneous Real-Time Systems / Houssam-Eddine, Z.; Capodieci, N.; Cavicchioli, R.; Lipari, G.; Bertogna, M.. - In: IEEE TRANSACTIONS ON COMPUTERS. - ISSN 0018-9340. - 70:10(2021), pp. 1747-1761. [10.1109/TC.2020.3023169]

The HPC-DAG Task Model for Heterogeneous Real-Time Systems

Capodieci N.;Cavicchioli R.;Bertogna M.
2021

Abstract

Recent commercial hardware platforms for embedded real-time systems feature heterogeneous processing units and computing accelerators on the same System-on-Chip. When designing complex real-time applications for such architectures, the designer is exposed to a number of difficult choices, like deciding on which compute engine to execute a certain task, or what degree of parallelism to adopt for a given function. To help the designer exploring the wide space of design choices and tune the scheduling parameters, we propose a novel real-time application model, called HPC-DAG (Heterogeneous Parallel Condition Directed Acyclic Graph Model), specifically conceived for heterogeneous platforms. An HPC-DAG allows the system designer to specify alternative implementations of a software component for different processing engines, as well as conditional branches to model if-then-else statements. We also propose a schedulability analysis for the HPC-DAG model and a set of heuristic allocation algorithms aimed at improving schedulability for latency sensitive applications. Our analysis takes into account the cost of preempting a task, which can be non-negligible on certain processors. We show the use of our approach on a realistic case study, and we demonstrate its effectiveness by comparing it with state-of-the-art algorithms previously proposed in literature.
2021
70
10
1747
1761
The HPC-DAG Task Model for Heterogeneous Real-Time Systems / Houssam-Eddine, Z.; Capodieci, N.; Cavicchioli, R.; Lipari, G.; Bertogna, M.. - In: IEEE TRANSACTIONS ON COMPUTERS. - ISSN 0018-9340. - 70:10(2021), pp. 1747-1761. [10.1109/TC.2020.3023169]
Houssam-Eddine, Z.; Capodieci, N.; Cavicchioli, R.; Lipari, G.; Bertogna, M.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1253758
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