In this work, we demonstrate FDSOI ferroelectric FETs (FeFETs) incorporating 4.5 nm hafnium zirconium oxide, which show a 0.5V memory window at +/-3.3V and a program/erase speed of 1 u s. In typical FeFETs where geq 9 nm thick ferroelectric (FE) gate oxides have been used, bulk charge trapping has been identified as the main mechanism for endurance degradation and shrinkage of the memory window (MW). By contrast, we find that the role of bulk trapping in our devices with a much thinner FE layer is minimal. Through a combination of cryogenic temperature-dependent electrical measurements and simulations using the Ginestra ™ modeling platform, we identify and prove that hot electron-induced hole damage during the application of negative gate biases is the primary source of endurance degradation and MW closure in FeFETs with scaled oxide layers.

Hot Electrons as the Dominant Source of Degradation for Sub-5nm HZO FeFETs / Tan, A. J.; Pesic, M.; Larcher, L.; Liao, Y. -H.; Wang, L. -C.; Bae, J. -H.; Hu, C.; Salahuddin, S.. - 2020-:(2020), pp. 1-2. (Intervento presentato al convegno 2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 tenutosi a usa nel 2020) [10.1109/VLSITechnology18217.2020.9265067].

Hot Electrons as the Dominant Source of Degradation for Sub-5nm HZO FeFETs

Larcher L.;
2020

Abstract

In this work, we demonstrate FDSOI ferroelectric FETs (FeFETs) incorporating 4.5 nm hafnium zirconium oxide, which show a 0.5V memory window at +/-3.3V and a program/erase speed of 1 u s. In typical FeFETs where geq 9 nm thick ferroelectric (FE) gate oxides have been used, bulk charge trapping has been identified as the main mechanism for endurance degradation and shrinkage of the memory window (MW). By contrast, we find that the role of bulk trapping in our devices with a much thinner FE layer is minimal. Through a combination of cryogenic temperature-dependent electrical measurements and simulations using the Ginestra ™ modeling platform, we identify and prove that hot electron-induced hole damage during the application of negative gate biases is the primary source of endurance degradation and MW closure in FeFETs with scaled oxide layers.
2020
2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020
usa
2020
2020-
1
2
Tan, A. J.; Pesic, M.; Larcher, L.; Liao, Y. -H.; Wang, L. -C.; Bae, J. -H.; Hu, C.; Salahuddin, S.
Hot Electrons as the Dominant Source of Degradation for Sub-5nm HZO FeFETs / Tan, A. J.; Pesic, M.; Larcher, L.; Liao, Y. -H.; Wang, L. -C.; Bae, J. -H.; Hu, C.; Salahuddin, S.. - 2020-:(2020), pp. 1-2. (Intervento presentato al convegno 2020 IEEE Symposium on VLSI Technology, VLSI Technology 2020 tenutosi a usa nel 2020) [10.1109/VLSITechnology18217.2020.9265067].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11380/1249296
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