Analysis of design methodology with logic cell arrays

Field Programmable Gale Arrays (FPGA) are becoming popular as an alternative to ASIC because of their good price/performance ratio in terms of speed and flexibility and ease of design implementation especially in the prototype phase. This paper analyses FPGA design both from the methodology and optimization techniques points of view. As an example the paper describes in detail the design optimization adopted for an array processor control unit which is characterized by a very large number of signals and repetitive architecture. The logic complexity and the corresponding simulation has led to choose an LCA (XIUNX) instead of a gate-array Ixised design. All design phases are discussed and a comparison with other design methodologies is presented.